CMRR is a display feature that uses adaptive sync framework to vary Vtotal slightly to match the content rate exactly without frame drops. This feature is a variation of VRR where it varies Vtotal slightly (between additional 0 and 1 Vtotal scanlines) to match content rate exactly without frame drops using the adaptive sync framework. enable this feature by programing new registers for CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the fractional part in (actual refresh rate/target refresh rate) * origVTotal. --v6: - CMRR handling in co-existatnce of LRR and DRRS - Correct vtotal paramas accuracy and add 2 digit precision. --v7: - Rebased patches in-accordance to AS SDP merge. - Add neccessary gaurd to prevent crtc_state mismatch during intel_vrr_get_config. -v8: - Add support for AS SDP for CMRR. - update palce holder for CMRR register(Jani). - Make CMRR as subset of FAVT, as per comments in patch#3. -v9: - Add CMRR register definitions to separate intel_vrr_reg.h. - Remove cmrr_enabling/disabling, use vrr.enable instead. - Update AS SDP pack function to accomodate target_rr_divider. - Remove duplicated lines to compute vrr_vsync params. - Set cmrr.enable with a separate patch at last. -v10: - Separate VRR related register definitions. - Add dependency header intel_display_reg_defs.h. - Rename file name to intel_vrr_regs.h instead of reg.h. - Revert removed line. - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly. - is_edp is not required inside is_cmrr_frac_required function. - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. - target_rr_divider is bools so handle accordingly. -v11: - Move VRR related register and bits to separate file intel_vrr_regs.h. - Correct file header macro to intel_vrr_regs.h. - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing. - Replace vrr.enable flag to cmrr.enable where added mistakenly. - Move cmrr computation patch to last and set other other required params before computing cmrr.enable. Mitul Golani (8): drm/i915: Separate VRR related register definitions drm/i915: Define and compute Transcoder CMRR registers drm/i915: Update trans_vrr_ctl flag when cmrr is computed drm/dp: Add refresh rate divider to struct representing AS SDP drm/i915/display: Add support for pack and unpack drm/i915/display: Compute Adaptive sync SDP params drm/i915/display: Compute vrr vsync params drm/i915: Compute CMRR and calculate vtotal drivers/gpu/drm/i915/display/intel_display.c | 24 +++- .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/display/intel_dp.c | 19 ++- drivers/gpu/drm/i915/display/intel_vrr.c | 128 +++++++++++++++-- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 129 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 100 -------------- include/drm/display/drm_dp_helper.h | 1 + 8 files changed, 289 insertions(+), 119 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h -- 2.25.1
