== Series Details == Series: Implement CMRR Support (rev10) URL : https://patchwork.freedesktop.org/series/126443/ State : warning == Summary == Error: dim checkpatch failed 8941224bb0a7 drm/i915: Separate VRR related register definitions -:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #24: new file mode 100644 -:42: ERROR:CODE_INDENT: code indent should use tabs where possible #42: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:14: + _TRANS_VRR_VSYNC_A)$ -:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line #42: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:14: + _TRANS_VRR_VSYNC_A)$ -:129: ERROR:CODE_INDENT: code indent should use tabs where possible #129: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:101: + _TRANS_VRR_VTOTAL_PREV_A)$ -:129: WARNING:LEADING_SPACE: please, no spaces at the start of a line #129: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:101: + _TRANS_VRR_VTOTAL_PREV_A)$ total: 2 errors, 3 warnings, 0 checks, 230 lines checked 096a2a62a58c drm/i915: Define and compute Transcoder CMRR registers -:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects? #52: FILE: drivers/gpu/drm/i915/display/intel_display.c:5044: +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) -:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #52: FILE: drivers/gpu/drm/i915/display/intel_display.c:5044: +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) total: 0 errors, 0 warnings, 2 checks, 118 lines checked 4203af585c18 drm/i915: Update trans_vrr_ctl flag when cmrr is computed 3dede228e5e5 drm/i915: Compute CMRR and calculate vtotal 59040f50b24f drm/dp: Add refresh rate divider to struct representing AS SDP 2fbe9ec90ddd drm/i915/display: Add support for pack and unpack c8b5e6951a06 drm/i915/display: Compute Adaptive sync SDP params -:43: ERROR:SPACING: space required before the open brace '{' #43: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2648: + } else{ total: 1 errors, 0 warnings, 0 checks, 31 lines checked 11e05c6ee4bd drm/i915/display: Compute vrr vsync params
