Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.
However, first we need to revert the patch that disables fastset
for C10.
Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx>
Mika Kahola (2):
drm/i915/display: Revert "drm/i915/display: Skip C10 state
verification in case of fastset"
drm/i915/display: Add compare config for MTL+ platforms
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 77 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 39 ++++++++++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
4 files changed, 116 insertions(+), 3 deletions(-)
--
2.34.1
