There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2a18ef974221..bcd0f2c8cb5c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -929,6 +929,18 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_psr *psr = &intel_dp->psr;
+ enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+
+ if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
+ u32 val = LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
+
+ if (intel_dp->psr.req_psr2_sdp_prior_scanline)
+ val |= EDP_PSR2_SU_SDP_SCANLINE;
+
+ intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),
+ val);
+ }
intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
--
2.34.1
