On Mon, Oct 21, 2013 at 07:16:24PM +0300, Ville Syrjälä wrote: > On Mon, Oct 21, 2013 at 05:26:38PM +0200, Daniel Vetter wrote: > > Really simple, and we don't even have working frame numbers. > > > > v2: Actually enable it ... > > > > v3: Review from Ville: > > - Unconditionally enable the border in the CRC checksum for > > consistency with gen3+. > > - Handle the "none" source to be able to disable the CRC machinery > > again. > > > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Thanks for your review, I've merged all the patches to dinq. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
