> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni
> Högander
> Sent: Friday, May 3, 2024 11:36 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH 3/3] drm/i915/psr: PSR2_CTL[Block Count Number] no needed
> for LunarLake
Nit: s/no/not
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>
> PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it.
>
> Bspec: 69885
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4d67a384e149..5ebfe4244d51 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -869,7 +869,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>
> val |= intel_psr2_get_tp_time(intel_dp);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 12 && DISPLAY_VER(dev_priv) < 20) {
> if (psr2_block_count(intel_dp) > 2)
> val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
> else
> --
> 2.34.1
