On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
> just call intel_de_write_fw() directly.
>
> This is prep work towards DSB based plane updates where these
> wrappers are more of a hinderance.
>
> Done with cocci mostly:
> @@
> expression D, R, L;
> @@
> - skl_write_wm_level(D, R, L)
> + intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
>
> @@
> expression D, R, B;
> @@
> - skl_ddb_entry_write(D, R, B)
> + intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 57 ++++++++------------
> 1 file changed, 22 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8a0a26ab8e6a..1daceb8ef9de 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> PLANE_BUF_START(entry->start);
> }
>
> -static void skl_ddb_entry_write(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_ddb_entry *entry)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> -}
> -
> static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
> @@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> return val;
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_wm_level *level)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> -}
> -
> void skl_write_plane_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
> - skl_plane_wm_level(pipe_wm, plane_id, level));
> + intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
> - skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> - skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
> - &wm->sagv.wm0);
> - skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> - &wm->sagv.trans_wm);
> + intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> + skl_plane_wm_reg_val(&wm->sagv.wm0));
> + intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> - skl_ddb_entry_write(i915,
> - PLANE_BUF_CFG(pipe, plane_id), ddb);
> + intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb));
>
> if (DISPLAY_VER(i915) < 11)
> - skl_ddb_entry_write(i915,
> - PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
> + intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb_y));
> }
>
> void skl_write_cursor_wm(struct intel_plane *plane,
> @@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, CUR_WM(pipe, level),
> - skl_plane_wm_level(pipe_wm, plane_id, level));
> + intel_de_write_fw(i915, CUR_WM(pipe, level),
> + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
> - skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> - skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
> - &wm->sagv.wm0);
> - skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
> - &wm->sagv.trans_wm);
> + intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> + skl_plane_wm_reg_val(&wm->sagv.wm0));
> + intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> + skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> - skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb);
> + intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> + skl_plane_ddb_reg_val(ddb));
> }
>
> static bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
Jani Nikula, Intel
