On Thu, 09 May 2024, Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx> wrote: > Add register definitions for Transcoder Fixed Average > Vtotal mode/CMRR function, with the necessary bitfields. > Compute these registers when CMRR is enabled, extending > Adaptive refresh rate capabilities. > > --v2: > - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] > - Fix indent and order based on register offset. [Jani] How does this match with... > > +#define _TRANS_CMRR_M_LO_A 0x604F0 > +#define _TRANS_CMRR_M_HI_A 0x604F4 > +#define _TRANS_CMRR_N_LO_A 0x604F8 > +#define _TRANS_CMRR_N_HI_A 0x604FC > +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A) > +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A) > +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A) > +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A) > + ...this? Please read the comment at the top of i915_reg.h BR, Jani. > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA _MMIO(0xe1100) -- Jani Nikula, Intel
