On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > A couple of PLANE_WM bits were still using the hand > rolled (1<<N) form. Replace with REG_BIT(). > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 0ad14727e334..8ef9bd50d021 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -300,8 +300,8 @@ > _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4) > > #define _PLANE_WM_1_A_0 0x70240 > -#define PLANE_WM_EN (1 << 31) > -#define PLANE_WM_IGNORE_LINES (1 << 30) > +#define PLANE_WM_EN REG_BIT(31) > +#define PLANE_WM_IGNORE_LINES REG_BIT(30) > #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) > #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) > #define _PLANE_WM_1_B_0 0x71240 -- Jani Nikula, Intel
