Hi Sima and Dave, Here goes our last pull request towards 6.10. drm-intel-next-2024-04-24: Core Changes: - Some DP/DP_MST DRM helpers (Imre) Driver Changes (i915 Display): - PLL refactoring (Ville) - Limit eDP MSO pipe only for display version 20 (Luca) - More display refactor towards independence from i915 dev_priv (Jani) - QGV/SAGV related refactor (Stanislav) - Few MTL/DSC and a UHBR monitor fix (Imre) - BXT/GLK per-lane vswing and PHY reg cleanup (Ville) The following changes since commit 700c34019555392a348f8c03237c1ebb5bf53eb4: drm/i915/display: tie DMC wakelock to DC5/6 state transitions (2024-04-17 11:41:23 +0300) are available in the Git repository at: https://anongit.freedesktop.org/git/drm/drm-intel tags/drm-intel-next-2024-04-24 for you to fetch changes up to 6068bc209ac8d07a5d04e93f168465195e22a4cc: drm/i915/dsi: pass display to register macros instead of implicit variable (2024-04-23 17:00:14 +0300) ---------------------------------------------------------------- Core Changes: - Some DP/DP_MST DRM helpers (Imre) Driver Changes (i915 Display): - PLL refactoring (Ville) - Limit eDP MSO pipe only for display version 20 (Luca) - More display refactor towards independence from i915 dev_priv (Jani) - QGV/SAGV related refactor (Stanislav) - Few MTL/DSC and a UHBR monitor fix (Imre) - BXT/GLK per-lane vswing and PHY reg cleanup (Ville) ---------------------------------------------------------------- Imre Deak (11): drm/i915/dp: Fix DSC line buffer depth programming drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit drm/dp: Add drm_dp_128b132b_supported() drm/dp_mst: Factor out drm_dp_mst_port_is_logical() drm/dp_mst: Add drm_dp_mst_aux_for_parent() drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates Jani Nikula (19): drm/i915: use system include for drm headers drm/i915/display: add intel_display -> drm_device backpointer drm/i915/display: add generic to_intel_display() macro drm/i915: add generic __to_intel_display() drm/i915/display: accept either i915 or display for feature tests drm/i915/quirks: convert struct drm_i915_private to struct intel_display drm/i915/display: rename __intel_wait_for_register_nowl() to indicate intel_de_ drm/i915/dmc: convert dmc wakelock interface to struct intel_display drm/i915/de: allow intel_display and drm_i915_private for de functions drm/i915/dmc: use struct intel_display more drm/i915/dmc: handle request_firmware() errors separately drm/i915/dmc: improve firmware parse failure propagation drm/i915/dmc: split out per-platform firmware path selection drm/i915/dmc: change how to disable DMC firmware using module param drm/i915/display: move dmc_firmware_path to display params drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definition drm/i915/dsi: add VLV_ prefix to VLV only register macros drm/i915/dsi: unify connector/encoder type and name usage drm/i915/dsi: pass display to register macros instead of implicit variable Luca Coelho (1): drm/i915: limit eDP MSO pipe only for display version 20 and below Stanislav Lisovskiy (4): drm/i915/display: Add meaningful traces for QGV point info error handling drm/i915/display: Extract code required to calculate max qgv/psf gv point drm/i915/display: Disable SAGV on bw init, to force QGV point recalculation drm/i915/display: handle systems with duplicate psf gv points Ville Syrjälä (26): drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state() drm/i915: Use printer for the rest of PLL debugfs dump drm/i915: Rename PLL hw_state variables/arguments drm/i915: Introduce some local PLL state variables drm/i915: Extract ilk_fb_cb_factor() drm/i915: Extract ilk_dpll_compute_fp() drm/i915: Extract i9xx_dpll_get_hw_state() drm/i915: Pass the PLL hw_state to pll->enable() drm/i915: Extract i965_dpll_md() drm/i915: Extract {i9xx,i8xx,ilk,vlv,chv}_dpll() drm/i915: Inline {i9xx,ilk}_update_pll_dividers() drm/i915: Modernize i9xx_pll_refclk() drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get() drm/i915: s/pipe_config/crtc_state/ in legacy PLL code drm/i915: Add local DPLL 'hw_state' variables drm/i915: Carve up struct intel_dpll_hw_state drm/i915: Unionize dpll_hw_state drm/i915: Suck snps/cx0 PLL states into dpll_hw_state drm/i915/dpio: Clean up bxt/glk PHY registers drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk drm/i915/dpio: Extract bxt_dpio_phy_regs.h drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp() drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff drm/i915/dpio: Program bxt/glk PHY TX registers per-lane drm/i915: Enable per-lane DP drive settings for bxt/glk Vinod Govindapillai (2): drm/i915/display: extract code to prepare qgv points mask drm/i915/display: force qgv check after the hw state readout drivers/gpu/drm/display/drm_dp_helper.c | 2 + drivers/gpu/drm/display/drm_dp_mst_topology.c | 22 +- drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h | 273 ++++++++++++ drivers/gpu/drm/i915/display/intel_backlight.c | 40 +- drivers/gpu/drm/i915/display/intel_bw.c | 160 +++++-- drivers/gpu/drm/i915/display/intel_bw.h | 6 + drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 +- drivers/gpu/drm/i915/display/intel_ddi.c | 33 +- drivers/gpu/drm/i915/display/intel_de.h | 157 ++++--- drivers/gpu/drm/i915/display/intel_display.c | 38 +- .../drm/i915/display/intel_display_conversion.h | 22 + drivers/gpu/drm/i915/display/intel_display_core.h | 3 + .../gpu/drm/i915/display/intel_display_debugfs.c | 39 +- .../gpu/drm/i915/display/intel_display_device.c | 3 + .../gpu/drm/i915/display/intel_display_device.h | 5 +- .../gpu/drm/i915/display/intel_display_driver.c | 5 +- .../gpu/drm/i915/display/intel_display_params.c | 4 + .../gpu/drm/i915/display/intel_display_params.h | 1 + .../drm/i915/display/intel_display_power_well.c | 24 +- drivers/gpu/drm/i915/display/intel_display_types.h | 80 ++-- drivers/gpu/drm/i915/display/intel_dmc.c | 179 +++++--- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 72 +-- drivers/gpu/drm/i915/display/intel_dmc_wl.h | 12 +- drivers/gpu/drm/i915/display/intel_dp.c | 18 +- .../gpu/drm/i915/display/intel_dp_link_training.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 106 +++-- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 213 +++++---- drivers/gpu/drm/i915/display/intel_dpio_phy.h | 48 +- drivers/gpu/drm/i915/display/intel_dpll.c | 328 ++++++++------ drivers/gpu/drm/i915/display/intel_dpll.h | 12 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 488 ++++++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 80 +++- drivers/gpu/drm/i915/display/intel_panel.c | 10 +- drivers/gpu/drm/i915/display/intel_pch_display.c | 4 +- drivers/gpu/drm/i915/display/intel_pps.c | 6 +- drivers/gpu/drm/i915/display/intel_quirks.c | 56 +-- drivers/gpu/drm/i915/display/intel_quirks.h | 6 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 6 +- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- drivers/gpu/drm/i915/display/skl_watermark.h | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c | 467 ++++++++++---------- drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 22 +- drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 327 +++++++------- drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 7 +- drivers/gpu/drm/i915/gvt/mmio.c | 1 + drivers/gpu/drm/i915/i915_params.c | 3 - drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 262 ----------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 19 +- drivers/gpu/drm/i915/soc/intel_dram.c | 2 + drivers/gpu/drm/xe/xe_device_types.h | 3 - include/drm/display/drm_dp_helper.h | 6 + include/drm/display/drm_dp_mst_helper.h | 7 + include/drm/display/drm_dsc.h | 3 - include/drm/i915_component.h | 2 +- 56 files changed, 2067 insertions(+), 1652 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h create mode 100644 drivers/gpu/drm/i915/display/intel_display_conversion.h
