On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address > does kinda look like it goes to the PLL block on a first glance, > but broadcast is special and doesn't even exist for the PLL > (only PCS and TX have it). > > The fact that we use a broadcast write here is a bit sketchy > IMO since we're now blasting the register to all PCS splines > across the whole PHY. So the PCS registers in the other channel > (ie. other pipe/port) will also be written. But I guess the > fact that we always write the same value should make this a nop > even if the other channel is already enabled (assuming the VBIOS/GOP > didn't screw up and use some other value...). > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I'll take your word for it. The patch does what the commit message says, Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c > index 6693beafe9c0..7e8aca3c87ec 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c > @@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) > vlv_pllb_recal_opamp(dev_priv, phy); > > /* Set up Tx target for periodic Rcomp update */ > - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f); > + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); > > /* Disable target IRef on PLL */ > reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe)); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a2fadcbe0932..8f3c83d2ab8d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -233,7 +233,6 @@ > #define _VLV_PLL_DW8_CH1 0x8060 > #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) > > -#define VLV_PLL_DW9_BCAST 0xc044 > #define _VLV_PLL_DW9_CH0 0x8044 > #define _VLV_PLL_DW9_CH1 0x8064 > #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) > @@ -370,6 +369,8 @@ > #define _VLV_PCS_DW14_CH1 0x8438 > #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) > > +#define VLV_PCS_DW17_BCAST 0xc044 > + > #define _VLV_PCS_DW23_CH0 0x825c > #define _VLV_PCS_DW23_CH1 0x845c > #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) -- Jani Nikula, Intel
