✓ Fi.CI.BAT: success for Enable display support for Battlemage

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Title: Project List - Patchwork
Patch Details
Series:Enable display support for Battlemage
URL:https://patchwork.freedesktop.org/series/132429/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v1/index.html

CI Bug Log - changes from CI_DRM_14581 -> Patchwork_132429v1

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132429v1/index.html

Participating hosts (40 -> 35)

Additional (1): fi-kbl-8809g
Missing (6): fi-kbl-7567u bat-kbl-2 fi-snb-2520m bat-atsm-1 fi-cfl-8109u bat-dg2-11

Known issues

Here are the changes found in Patchwork_132429v1 that come from known issues:

IGT changes

Issues hit

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_14581: 1bfe3965a846936d93b6e69385e53f1bd1c3b889 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7806: 849cd963ce7e8222dcf17cc872d355181fd2c2a2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_132429v1: 1bfe3965a846936d93b6e69385e53f1bd1c3b889 @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

a9a74fd0d3db drm/xe/bmg: Enable the display support
f6aedec08694 drm/i915/display: perform transient flush
38fe9c18ce21 drm/xe/device: implement transient flush
ed4af6e3fbb3 drm/xe/gt_print: add xe_gt_err_once()
b1ba13fed013 drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
ebd0d96dbd78 Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
2d7604adfcdb drm/i915/bmg: BMG should re-use MTL's south display logic
6045c39d3217 drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
081828c17080 drm/i915/xe2hpd: Add max memory bandwidth algorithm
6d11baa59a68 drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes
5e3db73be1db drm/i915/xe2hpd: Add display info
b4594af28b45 drm/i915/xe2hpd: update pll values in sync with Bspec
5f63e2074985 drm/i915/xe2hpd: Add support for eDP PLL configuration
e366fb899ef9 drm/i915/xe2hpd: Add new C20 PHY SRAM address
23401c7a8eb2 drm/i915/xe2hpd: Properly disable power in port A
32381c24b73b drm/i915/bmg: Extend DG2 tc check to future
8db752b0d565 drm/i915/xe2hpd: Initial cdclk table
dd8aa865d0df drm/i915/xe2hpd: Skip CCS modifiers
22fb2d0ede3e drm/i915/bmg: Define IS_BATTLEMAGE macro
790f17a1c672 drm/i915/display: Enable RM timeout detection
eef40a14cbd5 drm/xe/display: Lane reversal requires writes to both context lanes


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