> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Sent: Wednesday, April 3, 2024 2:30 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Manna, Animesh <animesh.manna@xxxxxxxxx>; Hogander, Jouni
> <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v5 06/19] drm/i915/psr: Do not write registers/bits not
> applicable for panel replay
>
> Bspec is saying this
> mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask
> Hotplug] are used in panel replay mode.
>
> Status register: Only SRD_STATUS[SRD state] field is used in panel replay
> mode.
>
> Due to this stop writing and reading registers and bits not used by panel
> replay if panel replay is used.
>
> Bspec: 53370, 68920
>
> v2:
> - use intel_dp_is_edp with PSR_MASK register
> - handle LunarLake as well
> - hanle ALPM configuration as well
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 70 +++++++++++++++---------
> 1 file changed, 45 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d7547eefc2fa..b7538a4405b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 mask;
>
> + if (intel_dp->psr.panel_replay_enabled)
> + return;
> +
> mask = psr_irq_psr_error_bit_get(intel_dp);
> if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> mask |= psr_irq_post_exit_bit_get(intel_dp) | @@ -1783,7
> +1786,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> - u32 mask;
> + u32 mask = 0;
>
> /*
> * Only HSW and BDW have PSR AUX registers that need to be setup.
> @@ -1797,34 +1800,46 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
> * mask LPSP to avoid dependency on other drivers that might block
> * runtime_pm besides preventing other hw tracking issues now we
> * can rely on frontbuffer tracking.
> + *
> + * From bspec prior LunarLake:
> + * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
> are used in
> + * panel replay mode.
> + *
> + * From bspec beyod LunarLake:
> + * Panel Replay on DP: No bits are applicable
> + * Panel Replay on eDP: All bits are applicable
> */
> - mask = EDP_PSR_DEBUG_MASK_MEMUP |
> - EDP_PSR_DEBUG_MASK_HPD;
> + if (DISPLAY_VER(dev_priv) < 20 || intel_dp_is_edp(intel_dp))
> + mask = EDP_PSR_DEBUG_MASK_HPD;
>
> - /*
> - * For some unknown reason on HSW non-ULT (or at least on
> - * Dell Latitude E6540) external displays start to flicker
> - * when PSR is enabled on the eDP. SR/PC6 residency is much
> - * higher than should be possible with an external display.
> - * As a workaround leave LPSP unmasked to prevent PSR entry
> - * when external displays are active.
> - */
> - if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL_ULT(dev_priv))
> - mask |= EDP_PSR_DEBUG_MASK_LPSP;
> + if (intel_dp_is_edp(intel_dp)) {
> + mask |= EDP_PSR_DEBUG_MASK_MEMUP;
>
> - if (DISPLAY_VER(dev_priv) < 20)
> - mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + /*
> + * For some unknown reason on HSW non-ULT (or at least on
> + * Dell Latitude E6540) external displays start to flicker
> + * when PSR is enabled on the eDP. SR/PC6 residency is much
> + * higher than should be possible with an external display.
> + * As a workaround leave LPSP unmasked to prevent PSR
> entry
> + * when external displays are active.
> + */
> + if (DISPLAY_VER(dev_priv) >= 8 ||
> IS_HASWELL_ULT(dev_priv))
> + mask |= EDP_PSR_DEBUG_MASK_LPSP;
>
> - /*
> - * No separate pipe reg write mask on hsw/bdw, so have to unmask
> all
> - * registers in order to keep the CURSURFLIVE tricks working :(
> - */
> - if (IS_DISPLAY_VER(dev_priv, 9, 10))
> - mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> + if (DISPLAY_VER(dev_priv) < 20)
> + mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
>
> - /* allow PSR with sprite enabled */
> - if (IS_HASWELL(dev_priv))
> - mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE;
> + /*
> + * No separate pipe reg write mask on hsw/bdw, so have to
> unmask all
> + * registers in order to keep the CURSURFLIVE tricks working
> :(
> + */
> + if (IS_DISPLAY_VER(dev_priv, 9, 10))
> + mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> +
> + /* allow PSR with sprite enabled */
> + if (IS_HASWELL(dev_priv))
> + mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE;
> + }
>
> intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder),
> mask);
>
> @@ -1843,7 +1858,8 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
> intel_dp->psr.psr2_sel_fetch_enabled ?
> IGNORE_PSR2_HW_TRACKING : 0);
>
> - lnl_alpm_configure(intel_dp);
> + if (intel_dp_is_edp(intel_dp))
> + lnl_alpm_configure(intel_dp);
>
> /*
> * Wa_16013835468
> @@ -1884,6 +1900,9 @@ static bool psr_interrupt_error_check(struct
> intel_dp *intel_dp)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 val;
>
> + if (intel_dp->psr.panel_replay_enabled)
> + goto no_err;
> +
> /*
> * If a PSR error happened and the driver is reloaded, the
> EDP_PSR_IIR
> * will still keep the error set even after the reset done in the @@ -
> 1901,6 +1920,7 @@ static bool psr_interrupt_error_check(struct intel_dp
> *intel_dp)
> return false;
> }
>
> +no_err:
> return true;
> }
>
> --
> 2.34.1
