On Wed, 03 Apr 2024, Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx> wrote:
> Xe2_HPD has different address for C20 PLL registers. Enable the support
> to use the right PLL register address based on display version.
>
> Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
> MTL's display). According to the BSpec, currently, only Xe2_HPD has
> different offsets, so make sure it is the only display using them in the
> driver.
Even less of a fan of the register handling after seeing this patch.
BR,
Jani.
>
> Bspec: 67610
> Cc: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Cc: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +++++++++++++++++--
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 9 +++++++
> 2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index caaae5d3758e..6e4647859fc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -770,6 +770,17 @@ static struct intel_c20pll_reg mtl_c20_reg = {
> .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR
> };
>
> +static struct intel_c20pll_reg xe2hpd_c20_reg = {
> + .tx_cnt_a = XE2HPD_C20_A_TX_CNTX_CFG_ADDR,
> + .tx_cnt_b = XE2HPD_C20_B_TX_CNTX_CFG_ADDR,
> + .cmn_cnt_a = XE2HPD_C20_A_CMN_CNTX_CFG_ADDR,
> + .cmn_cnt_b = XE2HPD_C20_B_CMN_CNTX_CFG_ADDR,
> + .mplla_a = XE2HPD_C20_A_MPLLA_CFG_ADDR,
> + .mplla_b = XE2HPD_C20_B_MPLLA_CFG_ADDR,
> + .mpllb_a = XE2HPD_C20_A_MPLLB_CFG_ADDR,
> + .mpllb_b = XE2HPD_C20_B_MPLLB_CFG_ADDR,
> +};
> +
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> .clock = 162000,
> @@ -2166,19 +2177,29 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
> }
>
> +static struct intel_c20pll_reg *intel_c20_get_pll_reg(struct drm_i915_private *i915)
> +{
> + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> + return &xe2hpd_c20_reg;
> + else
> + return &mtl_c20_reg;
> +}
> +
> static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state)
> {
> bool cntx;
> intel_wakeref_t wakeref;
> int i;
> - struct intel_c20pll_reg *pll_reg = &mtl_c20_reg;
> + struct intel_c20pll_reg *pll_reg;
>
> wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> /* 1. Read current context selection */
> cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
>
> + pll_reg = intel_c20_get_pll_reg(to_i915(encoder->base.dev));
> +
> /* Read Tx configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> if (cntx)
> @@ -2353,7 +2374,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> u32 clock = crtc_state->port_clock;
> bool cntx;
> int i;
> - const struct intel_c20pll_reg *pll_reg = &mtl_c20_reg;
> + const struct intel_c20pll_reg *pll_reg;
>
> if (intel_crtc_has_dp_encoder(crtc_state))
> dp = true;
> @@ -2372,6 +2393,8 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> usleep_range(4000, 4100);
> }
>
> + pll_reg = intel_c20_get_pll_reg(i915);
> +
> /* 3. Write SRAM configuration context. If A in use, write configuration to B context */
> /* 3.1 Tx configuration */
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 882b98dc347b..8e5fd605b99e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -292,6 +292,15 @@ struct intel_c20pll_reg {
> #define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A
> #define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E
>
> +#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR 0xCF5E
> +#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR 0xCF5A
> +#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E
> +#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89
> +#define XE2HPD_C20_A_MPLLA_CFG_ADDR 0xCE58
> +#define XE2HPD_C20_B_MPLLA_CFG_ADDR 0xCE4D
> +#define XE2HPD_C20_A_MPLLB_CFG_ADDR 0xCCC2
> +#define XE2HPD_C20_B_MPLLB_CFG_ADDR 0xCCB6
> +
> /* C20 Phy VSwing Masks */
> #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
> #define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
--
Jani Nikula, Intel
