| Series: | Enable dislay support for Battlemage (rev2) |
| URL: | https://patchwork.freedesktop.org/series/131984/ |
| State: | success |
| Details: | https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/index.html |
CI Bug Log - changes from CI_DRM_14520 -> Patchwork_131984v2
Summary
SUCCESS
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131984v2/index.html
Participating hosts (39 -> 30)
Missing (9): bat-arls-4 fi-snb-2520m fi-glk-j4005 bat-atsm-1 fi-cfl-8109u bat-dg2-11 fi-bsw-nick bat-jsl-1 bat-arls-3
Known issues
Here are the changes found in Patchwork_131984v2 that come from known issues:
IGT changes
Issues hit
-
igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: PASS -> FAIL (i915#10378)
- bat-dg2-8: PASS -> FAIL (i915#10378)
-
igt@gem_lmem_swapping@parallel-random-engines:
-
igt@i915_pm_rps@basic-api:
-
igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> SKIP
-
igt@kms_frontbuffer_tracking@basic:
-
igt@kms_pipe_crc_basic@hang-read-crc:
-
igt@kms_pm_backlight@basic-brightness:
-
igt@kms_psr@psr-sprite-plane-onoff:
-
igt@kms_setmode@basic-clone-single-crtc:
-
igt@prime_vgem@basic-fence-flip:
-
igt@prime_vgem@basic-write:
Possible fixes
-
igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: WARN (i915#10436) -> PASS
-
igt@i915_selftest@live@hangcheck:
- bat-rpls-3: DMESG-WARN (i915#5591) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Build changes
- Linux: CI_DRM_14520 -> Patchwork_131984v2
CI-20190529: 20190529
CI_DRM_14520: 23e6199ddb938adf30f3174971cd36160b8f0ade @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7797: e88ebc17ec12b503aab380b08c1213af9cc7a97c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_131984v2: 23e6199ddb938adf30f3174971cd36160b8f0ade @ git://anongit.freedesktop.org/gfx-ci/linux
Linux commits
4ff3db4ed8c1 drm/xe/bmg: Enable the display support
e69341c4b894 drm/i915/display: perform transient flush
3c8d78f26025 drm/xe/device: implement transient flush
2f890f740e2d drm/xe/gt_print: add xe_gt_err_once()
5041e5e64b5a drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
62518c712575 drm/i915/bmg: BMG should re-use MTL's south display logic
e797b1751dac drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
0b7b2915da83 drm/i915/display: Enable RM timeout detection
dd9abbff34f3 drm/i915/xe2hpd: Add max memory bandwidth algorithm
e4c0bac1c385 drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
dcf3b7c48faf drm/xe/display: Lane reversal requires writes to both context lanes
957cc4dc737d drm/i915/xe2hpd: Add missing chicken bit register programming
d1ad3a0bec7a drm/i915/xe2hpd: Add display info
dcb20dea7d71 drm/i915/xe2hpd: update pll values in sync with Bspec
e4ccd3ff10b3 drm/i915/xe2hpd: Add support for eDP PLL configuration
fff6e736f2ac drm/i915/xe2hpd: Add new C20 PLL register address
f86b2ba7fbe8 drm/i915/xe2hpd: Properly disable power in port A
82796f452e15 drm/i915/bmg: Extend DG2 tc check to future
4cecdb06e2ec Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
e430451e09da drm/i915/xe2hpd: Initial cdclk table
ed1fc2916af9 drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
4f9fcbb557a2 drm/i915/bmg: Define IS_BATTLEMAGE macro
fcdf063db61f drm/xe/bmg: Define IS_BATTLEMAGE macro
9f50c01d575f drm/xe/bmg: Add BMG platform definition
a4133968d1b8 drm/i915/display: Prepare to handle new C20 PLL register address
