Quoting Ville Syrjala (2024-03-27 14:45:35-03:00)
>From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>Currently we just get a plain "Changing CDCLK to ..." in the
>logs. It would actually be interesting to see whether we're
>doing the programming during the pre or post plane phase of
>the commit. Include that information in the debug message.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++++-------------
> 1 file changed, 6 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 99d2657f29a7..98546f384023 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2434,18 +2434,9 @@ static void intel_pcode_notify(struct drm_i915_private *i915,
> ret);
> }
>
>-/**
>- * intel_set_cdclk - Push the CDCLK configuration to the hardware
>- * @dev_priv: i915 device
>- * @cdclk_config: new CDCLK configuration
>- * @pipe: pipe with which to synchronize the update
>- *
>- * Program the hardware based on the passed in CDCLK state,
>- * if necessary.
>- */
> static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
>- enum pipe pipe)
>+ enum pipe pipe, const char *context)
> {
> struct intel_encoder *encoder;
>
>@@ -2455,7 +2446,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
> return;
>
>- intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
>+ intel_cdclk_dump_config(dev_priv, cdclk_config, context);
>
> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>@@ -2623,7 +2614,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>
> drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>
>- intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe);
>+ intel_set_cdclk(i915, &cdclk_config, new_cdclk_state->pipe,
>+ "Pre changing CDCLK to");
> }
>
> /**
>@@ -2651,7 +2643,8 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>
> drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
>
>- intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe);
>+ intel_set_cdclk(i915, &new_cdclk_state->actual, new_cdclk_state->pipe,
>+ "Post changing CDCLK to");
> }
>
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
>--
>2.43.2
>
