From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
glk_pipe_scaler_clock_gating_wa() is messy. Clean it up via
intel_de_rmw(), and also just pass in the whole crtc so the
caller doesn't dance around so much.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 08705042b4f8..83474fcf4131 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1551,18 +1551,13 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
- enum pipe pipe, bool apply)
+static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
{
- u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
- if (apply)
- val |= mask;
- else
- val &= ~mask;
-
- intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
+ intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),
+ mask, enable ? mask : 0);
}
static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
@@ -1638,8 +1633,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
+ enum pipe hsw_workaround_pipe;
bool psl_clkgate_wa;
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
@@ -1677,7 +1672,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
- glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
+ glk_pipe_scaler_clock_gating_wa(crtc, true);
if (DISPLAY_VER(dev_priv) >= 9)
skl_pfit_enable(new_crtc_state);
@@ -1709,7 +1704,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (psl_clkgate_wa) {
intel_crtc_wait_for_next_vblank(crtc);
- glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
+ glk_pipe_scaler_clock_gating_wa(crtc, false);
}
/* If we change the relative order between pipe/planes enabling, we need
--
2.43.2
