== Series Details == Series: Disable automatic load CCS load balancing (rev12) URL : https://patchwork.freedesktop.org/series/129951/ State : warning == Summary == Error: dim checkpatch failed 6f6385b0a101 drm/i915/gt: Disable HW load balancing for CCS 9e580948c216 drm/i915/gt: Do not generate the command streamer for all the CCS f630774aa552 drm/i915/gt: Enable only one CCS for compute workload Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:37: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #37: new file mode 100644 -:111: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'cslice' may be better as '(cslice)' to avoid precedence issues #111: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1433: +#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) -:111: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ccs' may be better as '(ccs)' to avoid precedence issues #111: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:1433: +#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) total: 0 errors, 1 warnings, 2 checks, 89 lines checked
