2013/10/11 <ville.syrjala@xxxxxxxxxxxxxxx>: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Using the 5/6 DDB split make sense only when sprites are enabled. > So check that before we waste any cycles computing the merged > watermarks with the 5/6 DDB split. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 211a946..214a8de 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2958,7 +2958,8 @@ static void haswell_update_wm(struct drm_crtc *crtc) > ilk_wm_merge(dev, &max, &lp_wm_1_2); > > /* 5/6 split only in single pipe config on IVB+ */ > - if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active == 1) { > + if (INTEL_INFO(dev)->gen >= 7 && > + config.num_pipes_active == 1 && config.sprites_enabled) { > ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); > ilk_wm_merge(dev, &max, &lp_wm_5_6); > > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx