On Fri, Mar 08, 2024 at 01:00:39PM +0200, Jouni Högander wrote: > Increasing number of fast wake sync pulses seem to fix problems with > certain PSR panels. This should be ok for other panels as well as the eDP > specification allows 10...16 precharge pulses and we are still within that > range. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739 > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c > index 7e69be100d90..5dff1bc85d61 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c > @@ -145,7 +145,7 @@ static int intel_dp_aux_sync_len(void) > > int intel_dp_aux_fw_sync_len(void) > { > - int precharge = 10; /* 10-16 */ > + int precharge = 12; /* 10-16 */ This is still giving me allergies because Windows doesn't have anything like this. So the mystery is how does Windows work? This was an actual production machine I take it? Did we have look at the error bits in PSR2_DEBUG to see if there is some difference between the working and non-working values? Anyways, this at least needs a proper comment to explain why we're not usign the standard value. > int preamble = 8; > > return precharge + preamble; > -- > 2.34.1 -- Ville Syrjälä Intel
