Increasing number of fast wake sync pulses seem to fix problems with certain PSR panels. This should be ok for other panels as well as the eDP specification allows 10...16 precharge pulses and we are still within that range. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9739 Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index fad39b2e3022..4641c5bb8fb9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -145,7 +145,7 @@ static int intel_dp_aux_sync_len(void) static u8 intel_dp_aux_fw_sync_len(void) { - u8 precharge = 10; /* 10-16 */ + u8 precharge = 12; /* 10-16 */ u8 preamble = 8; return precharge + preamble; -- 2.34.1
