On Wed, Feb 14, 2024 at 05:27:20PM -0300, Gustavo Sousa wrote:
> Looks like the name and description of intel_cdclk_needs_modeset()
> became inaccurate as of commit 59f9e9cab3a1 ("drm/i915: Skip modeset for
> cdclk changes if possible"), when it became possible to update the cdclk
> without requiring disabling the pipes when only changing the cd2x
> divider was enough.
>
> Later on we also added the same type of support with squash and crawling
> with commit 25e0e5ae5610 ("drm/i915/display: Do both crawl and squash
> when changing cdclk"), commit d4a23930490d ("drm/i915: Allow cdclk
> squasher to be reconfigured live") and commit d62686ba3b54
> ("drm/i915/adl_p: CDCLK crawl support for ADL").
>
> As such, update that function's name and documentation to something more
> appropriate, since the real checks for requiring modeset are done
> elsewhere.
>
> v2:
> - Rename to intel_cdclk_clock_changed instead of
> intel_cdclk_params_changed. (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 13 ++++++-------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
> .../gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> 3 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 26200ee3e23f..0a331d9def17 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2233,16 +2233,15 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> }
>
> /**
> - * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> - * configurations requires a modeset on all pipes
> + * intel_cdclk_clock_changed - Check whether the clock changed
> * @a: first CDCLK configuration
> * @b: second CDCLK configuration
> *
> * Returns:
> - * True if changing between the two CDCLK configurations
> - * requires all pipes to be off, false if not.
> + * True if CDCLK changed in a way that requires re-programming and
> + * False otherwise.
> */
> -bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> +bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> return a->cdclk != b->cdclk ||
> @@ -2295,7 +2294,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
> static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> - return intel_cdclk_needs_modeset(a, b) ||
> + return intel_cdclk_clock_changed(a, b) ||
> a->voltage_level != b->voltage_level;
> }
>
> @@ -3202,7 +3201,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> drm_dbg_kms(&dev_priv->drm,
> "Can change cdclk cd2x divider with pipe %c active\n",
> pipe_name(pipe));
> - } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
> + } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
> &new_cdclk_state->actual)) {
> /* All pipes must be switched off while we change the cdclk. */
> ret = intel_modeset_all_pipes_late(state, "CDCLK change");
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 48fd7d39e0cd..fa301495e7f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -60,7 +60,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> -bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> +bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 47cd6bb04366..c4d48498e977 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -968,7 +968,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> drm_WARN_ON(&dev_priv->drm,
> - intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
> + intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw,
> &cdclk_config));
>
> gen9_assert_dbuf_enabled(dev_priv);
> --
> 2.43.0
--
Ville Syrjälä
Intel
