This series intends to add support for Plane Color Management for Intel platforms. This is based on the design which has been agreed upon by the community. Series implementing the design for generic DRM core has been sent out by Harry Wentland and is under review below: https://patchwork.freedesktop.org/series/123446/ The base work of above series is squashed under 1 patch and support for Intel platform is added on top of it. Any reviews on the original core design is expected to be done in Harry's series to avoid any forking of the discussion. We have added some changes/fixes to the Harry's core DRM changes, being put up as separate patches on top of squashed patch. These are expected to get included in the main series from Harry once agreed upon. Changes added on core design: 1. Below patches implement some fixes on original series drm: Add missing function declarations drm: handle NULL next colorop in drm_colorop_set_next_property drm: Fix error logging in set Color Pipeline 2. Implemented a HW capability property to expose segmented luts. drm: Add Color lut range attributes drm: Add Color ops capability property drm: Define helper to create color ops capability property drm: Define helper for adding capability property for 1D LUT This helps in generically defining the hardware lut capabilities, lut distribution, precision, segmented or PWL LUTS. 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: drm: Add Enhanced LUT precision structure drm: Add support for 3x3 CTM drm: Add 1D LUT color op On top of this base work for DRM core plane color pipeline design, implementation is done for Intel hardware platforms. Below patches include the same: drm/i915: Add identifiers for intel color blocks drm/i915: Add intel_color_op drm/i915/color: Add helper to allocate intel colorop drm/i915/color: Add helper to create intel colorop drm/i915/color: Create a transfer function color pipeline drm/i915/color: Add and attach COLORPIPELINE plane property drm/i915/color: Add framework to set colorop drm/i915/color: Add callbacks to set plane CTM drm/i915/color: Add framework to program PRE/POST CSC LUT FIXME: force disable legacy plane color properties for TGL and beyond drm/i915/color: Enable Plane Color Pipelines drm/i915: Define segmented Lut and add capabilities to colorop drm/i915/color: Add plane CTM callback for TGL and beyond drm/i915: Add register definitions for Plane Degamma drm/i915: Add register definitions for Plane Post CSC drm/i915/color: Program Pre-CSC registers drm/i915/xelpd: Program Plane Post CSC Registers Bhanu from Intel will be sending out the igt changes to help test the color pipeline implementation based on the current igt changes sent out by Harry. https://patchwork.freedesktop.org/series/123448/ Planned Next Steps: 1. Work with Harry and community and get DRM core changes for color pipeline merged. 2. Implement pipe color management (post blending) based on the current color pipeline design. 3. Work with compositor maintainers to get color processing implemented using display hardware, thereby avoid any GL or GPU shaders. Thanks to all the community maintainers and contributors who have helped to get this support in upstream Linux. Looking forward to collaborate, work together and get this merged. Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> Cc: Pekka Paalanen <pekka.paalanen@xxxxxxxxxxxxx> Cc: Simon Ser <contact@xxxxxxxxxxx> Cc: Harry Wentland <harry.wentland@xxxxxxx> Cc: Melissa Wen <mwen@xxxxxxxxxx> Cc: Jonas Ådahl <jadahl@xxxxxxxxxx> Cc: Sebastian Wick <sebastian.wick@xxxxxxxxxx> Cc: Shashank Sharma <shashank.sharma@xxxxxxx> Cc: Alexander Goins <agoins@xxxxxxxxxx> Cc: Joshua Ashton <joshua@xxxxxxxxx> Cc: Michel Dänzer <mdaenzer@xxxxxxxxxx> Cc: Aleix Pol <aleixpol@xxxxxxx> Cc: Xaver Hugl <xaver.hugl@xxxxxxxxx> Cc: Victoria Brekenfeld <victoria@xxxxxxxxxxxx> Cc: Sima <daniel@xxxxxxxx> Cc: Naseer Ahmed <quic_naseer@xxxxxxxxxxx> Cc: Christopher Braga <quic_cbraga@xxxxxxxxxxx> Cc: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx> Cc: Arthur Grillo <arthurgrillo@xxxxxxxxxx> Cc: Hector Martin <marcan@xxxxxxxxx> Cc: Liviu Dudau <Liviu.Dudau@xxxxxxx> Cc: Sasha McIntosh <sashamcintosh@xxxxxxxxxx> Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@xxxxxxxxx> Chaitanya Kumar Borah (16): drm: Add missing function declarations drm: handle NULL next colorop in drm_colorop_set_next_property drm: Fix error logging in set Color Pipeline drm: Add support for 3x3 CTM drm: Add 1D LUT color op drm/i915: Add identifiers for intel color blocks drm/i915: Add intel_color_op drm/i915/color: Add helper to allocate intel colorop drm/i915/color: Add helper to create intel colorop drm/i915/color: Create a transfer function color pipeline drm/i915/color: Add and attach COLORPIPELINE plane property drm/i915/color: Add framework to set colorop drm/i915/color: Add callbacks to set plane CTM drm/i915/color: Add framework to program PRE/POST CSC LUT FIXME: force disable legacy plane color properties for TGL and beyond drm/i915/color: Enable Plane Color Pipelines Harry Wentland (1): [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar (11): drm: Add Enhanced LUT precision structure drm: Add Color lut range attributes drm: Add Color ops capability property drm: Define helper to create color ops capability property drm: Define helper for adding capability property for 1D LUT drm/i915: Define segmented Lut and add capabilities to colorop drm/i915/color: Add plane CTM callback for TGL and beyond drm/i915: Add register definitions for Plane Degamma drm/i915: Add register definitions for Plane Post CSC drm/i915/color: Program Pre-CSC registers drm/i915/xelpd: Program Plane Post CSC Registers Documentation/gpu/rfc/color_pipeline.rst | 352 ++++++++ drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/drm_atomic.c | 147 ++++ drivers/gpu/drm/drm_atomic_helper.c | 12 + drivers/gpu/drm/drm_atomic_state_helper.c | 5 + drivers/gpu/drm/drm_atomic_uapi.c | 170 ++++ drivers/gpu/drm/drm_colorop.c | 335 ++++++++ drivers/gpu/drm/drm_ioctl.c | 7 + drivers/gpu/drm/drm_mode_config.c | 7 + drivers/gpu/drm/i915/display/intel_color.c | 562 ++++++++++++ drivers/gpu/drm/i915/display/intel_color.h | 16 + .../drm/i915/display/intel_display_limits.h | 13 + .../drm/i915/display/intel_display_types.h | 17 + .../drm/i915/display/skl_universal_plane.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 124 +++ drivers/gpu/drm/tests/Makefile | 4 +- drivers/gpu/drm/tests/drm_fixp_test.c | 69 ++ drivers/gpu/drm/vkms/Kconfig | 5 + drivers/gpu/drm/vkms/Makefile | 4 +- drivers/gpu/drm/vkms/tests/.kunitconfig | 4 + drivers/gpu/drm/vkms/tests/vkms_color_tests.c | 355 ++++++++ drivers/gpu/drm/vkms/vkms_colorop.c | 115 +++ drivers/gpu/drm/vkms/vkms_composer.c | 117 ++- drivers/gpu/drm/vkms/vkms_drv.h | 8 + drivers/gpu/drm/vkms/vkms_luts.c | 802 ++++++++++++++++++ drivers/gpu/drm/vkms/vkms_luts.h | 12 + drivers/gpu/drm/vkms/vkms_plane.c | 2 + include/drm/drm_atomic.h | 87 ++ include/drm/drm_atomic_uapi.h | 3 + include/drm/drm_color_mgmt.h | 23 + include/drm/drm_colorop.h | 274 ++++++ include/drm/drm_file.h | 7 + include/drm/drm_fixed.h | 18 + include/drm/drm_mode_config.h | 18 + include/drm/drm_plane.h | 10 + include/uapi/drm/drm.h | 18 + include/uapi/drm/drm_mode.h | 83 ++ 37 files changed, 3815 insertions(+), 10 deletions(-) create mode 100644 Documentation/gpu/rfc/color_pipeline.rst create mode 100644 drivers/gpu/drm/drm_colorop.c create mode 100644 drivers/gpu/drm/tests/drm_fixp_test.c create mode 100644 drivers/gpu/drm/vkms/tests/.kunitconfig create mode 100644 drivers/gpu/drm/vkms/tests/vkms_color_tests.c create mode 100644 drivers/gpu/drm/vkms/vkms_colorop.c create mode 100644 drivers/gpu/drm/vkms/vkms_luts.c create mode 100644 drivers/gpu/drm/vkms/vkms_luts.h create mode 100644 include/drm/drm_colorop.h -- 2.42.0
