On Thu, 08 Feb 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Limit the link rate to HBR3 or below (<=8.1Gbps) in SST mode. > UHBR (10Gbps+) link rates require 128b/132b channel encoding > which we have not yet hooked up into the SST/no-sideband codepaths. > > Cc: stable@xxxxxxxxxxxxxxx > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> My bad. I guess this is the smallest most isolated fix for stable. Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index ab415f41924d..5045c34a16be 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2356,6 +2356,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, > limits->min_rate = intel_dp_common_rate(intel_dp, 0); > limits->max_rate = intel_dp_max_link_rate(intel_dp); > > + /* FIXME 128b/132b SST support missing */ > + limits->max_rate = min(limits->max_rate, 810000); > + > limits->min_lane_count = 1; > limits->max_lane_count = intel_dp_max_lane_count(intel_dp); -- Jani Nikula, Intel
