> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Manna, Animesh <animesh.manna@xxxxxxxxx>; Hogander, Jouni
> <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled
> before link training
>
> Panel replay has to be enabled on sink side before link training. Take this into
> account in fastset check and in initial fastset check.
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
LGTM.
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
> drivers/gpu/drm/i915/display/intel_psr.h | 3 +++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7..b7e5b2774f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_CSC(output_csc);
> }
>
> + /*
> + * Panel replay has to be enabled before link training. PSR doesn't
> have
> + * this requirement -> check these only if using panel replay
> + */
> + if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> + PIPE_CONF_CHECK_BOOL(has_psr);
> + PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> + PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> + PIPE_CONF_CHECK_BOOL(has_panel_replay);
> + }
> +
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> if (dev_priv->display.dpll.mgr) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e7cda3162ea2..11143fb9b0f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> fastset = false;
> }
>
> + if (CAN_PANEL_REPLAY(intel_dp)) {
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s] Forcing full modeset to
> compute panel replay state\n",
> + encoder->base.base.id, encoder->base.name);
> + crtc_state->uapi.mode_changed = true;
> + fastset = false;
> + }
> +
> return fastset;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b905aee0ec81..24a80f47b84f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -192,9 +192,6 @@
> #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> (intel_dp)->psr.source_support)
>
> -#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> - (intel_dp)-
> >psr.source_panel_replay_support)
> -
> bool intel_encoder_can_psr(struct intel_encoder *encoder) {
> if (intel_encoder_is_dp(encoder) || encoder->type ==
> INTEL_OUTPUT_DP_MST) diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index b74382b38f4a..e687d7bdbb1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,9 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> + (intel_dp)-
> >psr.source_panel_replay_support)
> +
> bool intel_encoder_can_psr(struct intel_encoder *encoder); void
> intel_psr_init_dpcd(struct intel_dp *intel_dp); void
> intel_psr_enable_sink(struct intel_dp *intel_dp,
> --
> 2.34.1
