> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Manna, Animesh <animesh.manna@xxxxxxxxx>; Hogander, Jouni
> <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v3 05/21] drm/i915/psr: Do not update phy power state in
> case of panel replay
>
> Currently panel replay is supporting only main link on mode -> Do not update
> phy power state for panel replay.
>
> Bspec: 53370
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
LGTM.
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7b3290f4e0b4..893c72ea8cf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1681,13 +1681,15 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
> if (!psr_interrupt_error_check(intel_dp))
> return;
>
> - if (intel_dp->psr.panel_replay_enabled)
> + if (intel_dp->psr.panel_replay_enabled) {
> drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
> - else
> + } else {
> drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> intel_dp->psr.psr2_enabled ? "2" : "1");
>
> - intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
> + intel_snps_phy_update_psr_power_state(dev_priv, phy,
> true);
> + }
> +
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp, crtc_state);
> intel_dp->psr.enabled = true;
> @@ -1794,7 +1796,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> CLKGATE_DIS_MISC_DMASC_GATING_DIS,
> 0);
> }
>
> - intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> + if (!intel_dp->psr.panel_replay_enabled)
> + intel_snps_phy_update_psr_power_state(dev_priv, phy,
> false);
>
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
> --
> 2.34.1
