> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Manna, Animesh <animesh.manna@xxxxxxxxx>; Hogander, Jouni
> <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on
> panel replay as well
>
> Current code is setting only intel_crtc_state->has_panel_replay in panel
> replay case. There are lots of stuff behind intel_crtc_state->has_psr that is
> needed for panel replay as well. Instead of converting each check to has_psr
> || has_panel_replay set has_psr in case of panel replay as well. Code can
> then differentiate between psr and panel replay by using intel_crtc_state-
> >has_panel_replay.
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
LGTM.
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b9d2f6ceb568..d69fefc2a94d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1409,10 +1409,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>
> if (CAN_PANEL_REPLAY(intel_dp))
> crtc_state->has_panel_replay = true;
> - else
> - crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> - if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
> + crtc_state->has_psr = crtc_state->has_panel_replay ? true :
> + _psr_compute_config(intel_dp, crtc_state);
> +
> + if (!crtc_state->has_psr)
> return;
>
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> @@ -1439,7 +1440,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
> goto unlock;
>
> if (intel_dp->psr.panel_replay_enabled) {
> - pipe_config->has_panel_replay = true;
> + pipe_config->has_psr = pipe_config->has_panel_replay =
> true;
> } else {
> /*
> * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> @@ -2352,7 +2353,7 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
>
> - if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
> + if (!crtc_state->has_psr)
> return;
>
> for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> --
> 2.34.1
