✓ Fi.CI.BAT: success for drm/i915/dp: Add jitter WAs for MST/FEC/DSC links

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/dp: Add jitter WAs for MST/FEC/DSC links
URL:https://patchwork.freedesktop.org/series/129277/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/index.html

CI Bug Log - changes from CI_DRM_14192 -> Patchwork_129277v1

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/index.html

Participating hosts (37 -> 35)

Missing (2): bat-mtlp-8 fi-snb-2520m

Known issues

Here are the changes found in Patchwork_129277v1 that come from known issues:

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_14192: f4c0dac89bd3cd02a1afe5e7a91ed4bf8de4afc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7698: af750f5e7eaad98d40d8c924eb5f05e99d3c668b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129277v1: f4c0dac89bd3cd02a1afe5e7a91ed4bf8de4afc6 @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

684e00785693 drm/i915/mtl: Add DP FEC BS jitter WA
4710e5a9e439 drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA
f5853ef36adf drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)
58b3ea4c8782 drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)
a8501371285d drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)
b689adcd3028 drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)


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