For High refresh rates usages, Vblank is required to be really small.
It cannot accommodate PKGC exit delay after framestart. Block PKGC till
next framestart which will be set by software and later will be
cleared by HW at framestart.
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx>
Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 5 +++++
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c6680ee2127c..928db551c685 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7421,6 +7421,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
drm_atomic_helper_commit_hw_done(&state->base);
+ if (DISPLAY_VER(dev_priv) >= 20)
+ intel_dmc_block_pkgc(dev_priv);
+
if (state->modeset) {
/* As one of the primary mmio accessors, KMS has a high
* likelihood of triggering bugs in unclaimed access. After we
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 51e0463518fb..2f86fc5f5f32 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1247,3 +1247,18 @@ void intel_dmc_debugfs_register(struct drm_i915_private *i915)
debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
i915, &intel_dmc_debugfs_status_fops);
}
+
+void intel_dmc_block_pkgc(struct drm_i915_private *i915)
+{
+ u32 pkgc_ctrl;
+
+ if (HAS_DMC(i915)) {
+ pkgc_ctrl = intel_de_read(i915, DMC_BLOCK_PKGC);
+ pkgc_ctrl |= DMC_BLOCK_PKGC_ENABLE;
+ intel_de_write(i915, DMC_BLOCK_PKGC, pkgc_ctrl);
+ } else {
+ pkgc_ctrl = intel_de_read(i915, DMC_BLOCK_PKGC_SW);
+ pkgc_ctrl |= DMC_BLOCK_PKGC_ENABLE;
+ intel_de_write(i915, DMC_BLOCK_PKGC_SW, pkgc_ctrl);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index fd607afff2ef..6c2fcaea4c0d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -24,6 +24,7 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915);
void intel_dmc_debugfs_register(struct drm_i915_private *i915);
void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
struct drm_i915_private *i915);
+void intel_dmc_block_pkgc(struct drm_i915_private *i915);
void assert_dmc_loaded(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index cf10094acae3..2d52fe7f3450 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -80,6 +80,11 @@
#define ADLP_PIPE_MMIO_START 0x5F000
#define ADLP_PIPE_MMIO_END 0x5FFFF
+#define DMC_BLOCK_PKGC _MMIO(0x8F1C0)
+#define DMC_BLOCK_PKGC_SW _MMIO(0x8F1C4)
+
+#define DMC_BLOCK_PKGC_ENABLE REG_BIT(31)
+
#define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
_TGL_PIPEB_MMIO_START)
--
2.29.0
