> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH v2 04/13] drm/i915/psr: Unify panel replay enable sink
>
> Panel replay enable for a sink is currently done in
> intel_ddi.c:intel_ddi_pre_enable_dp. Move it to intel_psr_enable_sink to
> unify psr/panel replay paths. Also enable some additional hpd interrupts for
> panel replay.
There is a difference between psr and panel replay regarding sink enablement.
For panel replay sink need to be enabled before link training which is not same for psr.
Regards,
Animesh
>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +------
> drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++--
> 2 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 922194b957be..db2a027fc55e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2800,15 +2800,10 @@ static void intel_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> const struct drm_connector_state
> *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - if (HAS_DP20(dev_priv)) {
> + if (HAS_DP20(dev_priv))
> intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> crtc_state);
> - if (crtc_state->has_panel_replay)
> - drm_dp_dpcd_writeb(&intel_dp->aux,
> PANEL_REPLAY_CONFIG,
> - DP_PANEL_REPLAY_ENABLE);
> - }
>
> if (DISPLAY_VER(dev_priv) >= 14)
> mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a9421dd092c5..8157a1eac8c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -618,6 +618,16 @@ static bool psr2_su_region_et_valid(struct intel_dp
> *intel_dp)
> return false;
> }
>
> +static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> +*intel_dp) {
> + return intel_dp->psr.panel_replay_enabled ?
> + PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
> +}
> +
> +/*
> + * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and
> +DP_PSR_EN_CFG. We
> + * are relying on PSR definitions on these "common" bits.
> + */
> static void intel_psr_enable_sink(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 643,15 +653,20 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> + if (intel_dp->psr.panel_replay_enabled)
> + dpcd_val |=
> DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
> + DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
> +
> if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
>
> if (intel_dp->psr.entry_setup_frames > 0)
> dpcd_val |= DP_PSR_FRAME_CAPTURE;
>
> - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> +intel_psr_get_enable_sink_offset(intel_dp), dpcd_val);
>
> - drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> + if (intel_dp_is_edp(intel_dp))
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> }
>
> static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
> --
> 2.34.1
