On Thu, 2024-01-04 at 11:04 -0800, george.d.sworo@xxxxxxxxx wrote:
> From: George D Sworo <george.d.sworo@xxxxxxxxx>
>
> GOP driver in the firmware is masking the QGV points except the one
> which can
> provide high Bandwidth required for panel.
>
> On boot to the OS the mask is already set, and is not cleared
> anywhere
> in the i915 driver
> even though sagv is enabled. This means Pcode is unable to switch to
> other QGV work points
> except the one enabled by default in the GOP driver at boot time.
>
> This change resets the mask, when i915 driver is finding the QGV
> points at the boot time. So that Pcode can switch to QGV work points
> based
> on the Workloads.
>
> Signed-off-by: George D Sworo <george.d.sworo@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bef96db62c80..e2576c0fb729 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -212,6 +212,7 @@ static int icl_get_qgv_points(struct
> drm_i915_private *dev_priv,
> bool is_y_tile)
> {
> const struct dram_info *dram_info = &dev_priv->dram_info;
> + u32 val = 0x00, val2 = 0;
> int i, ret;
>
> qi->num_points = dram_info->num_qgv_points;
> @@ -311,6 +312,11 @@ static int icl_get_qgv_points(struct
> drm_i915_private *dev_priv,
> i, qi->psf_points[i].clk);
> }
>
> + /* clear the QGV points mask set by the GOP driver while
> booting */
> + ret = snb_pcode_read(&dev_priv->uncore,
> ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, &val, &val2);
> + if (ret)
> + return ret;
> +
> return 0;
> }
>
hi Stan,
Thanks for the quick reply. unfortunately, SAGV frequency doesnt seem
to be scaling even with this patch added
https://patchwork.freedesktop.org/series/126962/ .
Apologies, the first patch you replied to was sent with an email that
was not registered with intel-gfx. I had to resubmit.
