Re: [PATCH 1/3] drm/i915/gt: Support fixed CCS mode

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Quoting Andi Shyti (2023-12-21 19:08:22)
> The CCS mode involves assigning CCS engines to slices depending
> on the number of slices and the number of engines the user wishes
> to set.
> 
> In this patch, the default CCS setting is established during the
> initial GT settings. It involves assigning only one CCS to all
> the slices.
> 
> Based on a patch by Chris Wilson <chris.p.wilson@xxxxxxxxxxxxxxx>
> and Tejas Upadhyay <tejas.upadhyay@xxxxxxxxx>.
> 
> Signed-off-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris.p.wilson@xxxxxxxxxxxxxxx>
> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@xxxxxxxxx>
> Cc: Tejas Upadhyay <tejas.upadhyay@xxxxxxxxx>

<SNIP>

> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -207,6 +207,26 @@ struct intel_gt {
>                                             [MAX_ENGINE_INSTANCE + 1];
>         enum intel_submission_method submission_method;
>  
> +       /*
> +        * Track fixed mapping between CCS engines and compute slices.
> +        *
> +        * In order to w/a HW that has the inability to dynamically load
> +        * balance between CCS engines and EU in the compute slices, we have to
> +        * reconfigure a static mapping on the fly. We track the current CCS
> +        * configuration (determined by inspection of the user's engine
> +        * selection during execbuf) and compare it against the current
> +        * CCS_MODE (which maps CCS engines to compute slices).  If there is
> +        * only a single engine selected, we can map it to all available
> +        * compute slices for maximal single task performance (fast/narrow). If
> +        * there are more then one engine selected, we have to reduce the
> +        * number of slices allocated to each engine (wide/slow), fairly
> +        * distributing the EU between the equivalent engines.
> +        */

This comment is outdated as we don't consider execbuf but the sysfs
configuration.

Regards, Joonas

> +       struct {
> +               struct mutex mutex;
> +               u32 mode;
> +       } ccs;
> +
>         /*
>          * Default address space (either GGTT or ppGTT depending on arch).
>          *




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