On Wed, Dec 13, 2023 at 12:16:12PM +0530, Haridhar Kalvala wrote: > Enable Force Dispatch Ends Collection for DG2. > > BSpec: 46001 > > Signed-off-by: Haridhar Kalvala <haridhar.kalvala@xxxxxxxxx> > Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> Applied to drm-intel-gt-next. Thanks for the patch. Matt > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 9de41703fae5..50962cfd1353 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -469,6 +469,9 @@ > #define XEHP_PSS_MODE2 MCR_REG(0x703c) > #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > > +#define XEHP_PSS_CHICKEN MCR_REG(0x7044) > +#define FD_END_COLLECT REG_BIT(5) > + > #define GEN7_SC_INSTDONE _MMIO(0x7100) > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 4cbf9e512645..3eacbc50caf8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -777,6 +777,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > /* Wa_18019271663:dg2 */ > wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > + > + /* Wa_14019877138:dg2 */ > + wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); > } > > static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine, > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
