On Thu, Dec 14, 2023 at 07:26:29AM +0000, Shuicheng Lin wrote: > some of the wa registers are MCR registers, which has different > read/write process with normal MMIO registers. As the MCR process > also work for normal MMIO registers, change all wa registers to > MCR process for simplicity. > > Signed-off-by: Shuicheng Lin <shuicheng.lin@xxxxxxxxx> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 63724e17829a..7409d3255cb0 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -377,8 +377,12 @@ static int guc_mmio_regset_init(struct temp_regset *regset, > CCS_MASK(engine->gt)) > ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true); > > + /* some of the wa registers are MCR regiters */ > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) > - ret |= GUC_MMIO_REG_ADD(gt, regset, wa->reg, wa->masked_reg); > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) The condition here doesn't really make sense. MCR registers have existed since gen8, so why are we doing this on graphics version 12.50 and higher? It would be better to just make this conditional on whether the register is actually an MCR register (and needs special steering) or not. Matt > + ret |= GUC_MCR_REG_ADD(gt, regset, wa->mcr_reg, wa->masked_reg); > + else > + ret |= GUC_MMIO_REG_ADD(gt, regset, wa->reg, wa->masked_reg); > > /* Be extra paranoid and include all whitelist registers. */ > for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
