On Wed, Dec 13, 2023 at 12:25:19PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> This reverts commit cfeff354f70bb1d0deb0279506e3f7989bc16e28.
>
> A core design consideration with legacy cursor updates is that the
> cursor must not touch any other plane, even if we were to force it
> to take the slow path. That is the real reason why the cursor uses
> a fixed ddb allocation, not because bspec says so.
>
> Treating cursors as any other plane during ddb allocation
> violates that, which means we can now pull other planes into
> fully unsynced legacy cursor mailbox commits. That is
> definitely not something we've ever considered when designing
> the rest of the code. The noarm+arm register write split in
> particular makes that dangerous as previous updates can get
> disarmed pretty much at any random time, and not necessarily
> in an order that is actually safe (eg. against ddb overlaps).
>
> So if we were to do this then:
> - someone needs to expend the appropriate amount of brain
> cells thinking through all the tricky details
So question is how can we avoid pulling other planes to the commit?..
Stan
> - we should do it for all skl+ platforms since all
> of those have double buffered wm/ddb registers. The current
> arbitrary mtl+ cutoff doesn't really make sense
>
> For the moment just go back to the original behaviour where
> the cursor's ddb alloation does not change outside of
> modeset/fastset. As of now anything else isn't safe.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +++---
> drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++++++---------
> 2 files changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 06c2455bdd78..76d77d5a0409 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -217,6 +217,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
> int width, height;
> unsigned int rel_data_rate;
>
> + if (plane->id == PLANE_CURSOR)
> + return 0;
> +
> if (!plane_state->uapi.visible)
> return 0;
>
> @@ -244,9 +247,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>
> rel_data_rate = width * height * fb->format->cpp[color_plane];
>
> - if (plane->id == PLANE_CURSOR)
> - return rel_data_rate;
> -
> return intel_adjusted_rate(&plane_state->uapi.src,
> &plane_state->uapi.dst,
> rel_data_rate);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 56588d6e24ae..051a02ac01a4 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
> u64 data_rate = 0;
>
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
> + if (plane_id == PLANE_CURSOR)
> continue;
>
> data_rate += crtc_state->rel_data_rate[plane_id];
> @@ -1514,12 +1514,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - if (DISPLAY_VER(i915) < 20) {
> - cursor_size = skl_cursor_allocation(crtc_state, num_active);
> - iter.size -= cursor_size;
> - skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> - alloc->end - cursor_size, alloc->end);
> - }
> + cursor_size = skl_cursor_allocation(crtc_state, num_active);
> + iter.size -= cursor_size;
> + skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
> + alloc->end - cursor_size, alloc->end);
>
> iter.data_rate = skl_total_relative_data_rate(crtc_state);
>
> @@ -1533,7 +1531,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
> + if (plane_id == PLANE_CURSOR) {
> const struct skl_ddb_entry *ddb =
> &crtc_state->wm.skl.plane_ddb[plane_id];
>
> @@ -1581,7 +1579,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
> + if (plane_id == PLANE_CURSOR)
> continue;
>
> if (DISPLAY_VER(i915) < 11 &&
> --
> 2.41.0
>
