On Mon, 11 Dec 2023, Jani Nikula <jani.nikula@xxxxxxxxx> wrote: > On Tue, 05 Dec 2023, Jani Nikula <jani.nikula@xxxxxxxxx> wrote: >> The eDP 1.5 spec adds a clarification for eDP 1.4x: >> >>> For eDP v1.4x, if the Source device chooses the Main-Link rate by way >>> of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0]. >> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the panel >> to ignore the rate set method. >> >> Moreover, 0 is a reserved value for DP_LINK_BW_SET, and should not be >> used. >> >> v2: Improve the comments (Ville) >> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081 >> Tested-by: Animesh Manna <animesh.manna@xxxxxxxxx> >> Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> > > Pushed to drm-intel-next, thanks for the review and testing. Also picked up to drm-intel-fixes with cc: stable that I forgot to add. BR, Jani. > > BR, > Jani. > >> --- >> .../drm/i915/display/intel_dp_link_training.c | 31 +++++++++++++------ >> 1 file changed, 21 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c >> index dbc1b66c8ee4..1abfafbbfa75 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c >> @@ -650,19 +650,30 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp, >> const struct intel_crtc_state *crtc_state, >> u8 link_bw, u8 rate_select) >> { >> - u8 link_config[2]; >> + u8 lane_count = crtc_state->lane_count; >> >> - /* Write the link configuration data */ >> - link_config[0] = link_bw; >> - link_config[1] = crtc_state->lane_count; >> if (crtc_state->enhanced_framing) >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; >> + >> + if (link_bw) { >> + /* DP and eDP v1.3 and earlier link bw set method. */ >> + u8 link_config[] = { link_bw, lane_count }; >> >> - /* eDP 1.4 rate select method. */ >> - if (!link_bw) >> - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, >> - &rate_select, 1); >> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, >> + ARRAY_SIZE(link_config)); >> + } else { >> + /* >> + * eDP v1.4 and later link rate set method. >> + * >> + * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if >> + * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. >> + * >> + * eDP v1.5 sinks allow choosing either, and the last choice >> + * shall be active. >> + */ >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); >> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); >> + } >> } >> >> /* -- Jani Nikula, Intel
