> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@xxxxxxxxx>
> Sent: Friday, December 8, 2023 12:10 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@xxxxxxxxx>; Taylor, Clinton A <clinton.a.taylor@xxxxxxxxx>; Kahola, Mika
> <mika.kahola@xxxxxxxxx>
> Subject: [PATCH 1/3] drm/i915/mtl: Use port clock compatible numbers for C20 phy
>
> In C20 pll_state link_bit_rate and clock fields are bit redundant. Since many of the helpers assume the clock values, which are
> different from link_bit_rate for dp2.0, convert the helpers to use the numbers that are compatible with link_bit_rate.
>
> Currently link_bit_rate is compatible with crtc_state->port_clock. The function intel_c20pll_calc_port_clock returns the number
> which is compatible with crtc_state->port_clock. In order to avoid extra conversions b/ween clock and link_bit_rate, remove
> "clock" field from the
> C20 pll_state and then rename "link_bit_rate" as "clock".
>
> While at it rely on crtc_state->port_clock during C20 Pll programming.
>
> Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++----------
> 1 file changed, 22 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 5fbec5784b83..7d412be996ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2117,7 +2117,7 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, static bool intel_c20_use_mplla(u32
> clock) {
> /* 10G and 20G rates use MPLLA */
> - if (clock == 312500 || clock == 625000)
> + if (clock == 1000000 || clock == 2000000)
> return true;
>
> return false;
> @@ -2192,7 +2192,7 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
> hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
>
> - if (intel_c20_use_mplla(hw_state->clock)) {
> + if (intel_c20_use_mplla(hw_state->link_bit_rate)) {
> for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
> } else {
> @@ -2220,11 +2220,11 @@ static u8 intel_c20_get_dp_rate(u32 clock)
> return 6;
> case 432000: /* 4.32 Gbps eDP */
> return 7;
> - case 312500: /* 10 Gbps DP2.0 */
> + case 1000000: /* 10 Gbps DP2.0 */
> return 8;
> - case 421875: /* 13.5 Gbps DP2.0 */
> + case 1350000: /* 13.5 Gbps DP2.0 */
> return 9;
> - case 625000: /* 20 Gbps DP2.0*/
> + case 2000000: /* 20 Gbps DP2.0 */
> return 10;
> case 648000: /* 6.48 Gbps eDP*/
> return 11;
> @@ -2242,13 +2242,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
> return 0;
>
> switch (clock) {
> - case 166670: /* 3 Gbps */
> - case 333330: /* 6 Gbps */
> - case 666670: /* 12 Gbps */
> + case 300000: /* 3 Gbps */
> + case 600000: /* 6 Gbps */
> + case 1200000: /* 12 Gbps */
> return 1;
> - case 444440: /* 8 Gbps */
> + case 800000: /* 8 Gbps */
> return 2;
> - case 555560: /* 10 Gbps */
> + case 1000000: /* 10 Gbps */
> return 3;
> default:
> MISSING_CASE(clock);
> @@ -2259,7 +2259,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock) static bool is_dp2(u32 clock) {
> /* DP2.0 clock rates */
> - if (clock == 312500 || clock == 421875 || clock == 625000)
> + if (clock == 1000000 || clock == 1350000 || clock == 2000000)
> return true;
>
> return false;
> @@ -2268,11 +2268,11 @@ static bool is_dp2(u32 clock) static bool is_hdmi_frl(u32 clock) {
> switch (clock) {
> - case 166670: /* 3 Gbps */
> - case 333330: /* 6 Gbps */
> - case 444440: /* 8 Gbps */
> - case 555560: /* 10 Gbps */
> - case 666670: /* 12 Gbps */
> + case 300000: /* 3 Gbps */
> + case 600000: /* 6 Gbps */
> + case 800000: /* 8 Gbps */
> + case 1000000: /* 10 Gbps */
> + case 1200000: /* 12 Gbps */
> return true;
> default:
> return false;
> @@ -2305,6 +2305,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
> bool dp = false;
> int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
> + u32 clock = crtc_state->port_clock;
> bool cntx;
> int i;
>
> @@ -2343,7 +2344,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> }
>
> /* 3.3 mpllb or mplla configuration */
> - if (intel_c20_use_mplla(pll_state->clock)) {
> + if (intel_c20_use_mplla(clock)) {
> for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> if (cntx)
> intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, @@ -2370,23 +2371,23 @@
> static void intel_c20_pll_program(struct drm_i915_private *i915,
> /* 4. Program custom width to match the link protocol */
> intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
> PHY_C20_CUSTOM_WIDTH_MASK,
> - PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state->clock, dp)),
> + PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)),
> MB_WRITE_COMMITTED);
>
> /* 5. For DP or 6. For HDMI */
> if (dp) {
> intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
> - BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
> + BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),
> MB_WRITE_COMMITTED);
> } else {
> intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
> - is_hdmi_frl(pll_state->clock) ? BIT(7) : 0,
> + is_hdmi_frl(clock) ? BIT(7) : 0,
> MB_WRITE_COMMITTED);
>
> intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
> - intel_c20_get_hdmi_rate(pll_state->clock),
> + intel_c20_get_hdmi_rate(clock),
> MB_WRITE_COMMITTED);
> }
>
> --
> 2.34.1
