Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.
v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
disabled.
v3: - Move force disable function to intel_bw_init in order to initialize
bw state as well, so that hw/sw are immediately in sync after init.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_bw.c | 25 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_bw.h | 2 ++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index efd408e96e8a..7db28c6631fc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -844,7 +844,7 @@ static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
return max_bw_point;
}
-unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
+static unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
{
unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
unsigned int max_bw = 0;
@@ -863,6 +863,26 @@ unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
return max_bw_point;
}
+int icl_force_disable_sagv(struct drm_i915_private *i915, struct intel_bw_state *bw_state)
+{
+ unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
+ unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915);
+ unsigned int qgv_points;
+ unsigned int psf_points;
+
+ qgv_points = BIT(max_bw_qgv_point);
+ psf_points = BIT(max_bw_psf_gv_point);
+
+ bw_state->qgv_points_mask = ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+ icl_qgv_points_mask(i915);
+
+ drm_dbg_kms(&i915->drm, "Forcing SAGV disable: leaving QGV point %d, PSF GV %d\n",
+ max_bw_qgv_point, max_bw_psf_gv_point);
+
+ return icl_pcode_restrict_qgv_points(i915, bw_state->qgv_points_mask);
+}
+
static int mtl_find_qgv_points(struct drm_i915_private *i915,
unsigned int data_rate,
unsigned int num_active_planes,
@@ -1373,5 +1393,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
&state->base, &intel_bw_funcs);
+ if (DISPLAY_VER(dev_priv) < 14)
+ icl_force_disable_sagv(dev_priv, state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 59cb4fc5db76..d6eb771baea1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -74,5 +74,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
bool *need_cdclk_calc);
int intel_bw_min_cdclk(struct drm_i915_private *i915,
const struct intel_bw_state *bw_state);
+int icl_force_disable_sagv(struct drm_i915_private *dev_priv,
+ struct intel_bw_state *bw_state);
#endif /* __INTEL_BW_H__ */
--
2.37.3
