On Tue, Nov 28, 2023 at 02:22:23PM +0200, Jani Nikula wrote: > On Mon, 27 Nov 2023, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Apparently some BXT/GLK systems have DSI panels whose timings > > don't agree with the normal cpu transcoder hblank>=32 limitation. > > This is perhaps fine as there are no specific hblank/etc. limits > > listed for the BXT/GLK DSI transcoders. > > > > Move those checks out from the global intel_mode_valid() into > > into connector specific .mode_valid() hooks, skipping BXT/GLK > > DSI connectors. We'll leave the basic [hv]display/[hv]total > > checks in intel_mode_valid() as those seem like sensible upper > > limits regardless of the transcoder used. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9720 > > Fixes: 8f4b1068e7fc ("drm/i915: Check some transcoder timing minimum limits") > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/display/icl_dsi.c | 7 +++++++ > > drivers/gpu/drm/i915/display/intel_crt.c | 5 +++++ > > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++++ > > drivers/gpu/drm/i915/display/intel_display.h | 3 +++ > > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++++ > > drivers/gpu/drm/i915/display/intel_dvo.c | 6 ++++++ > > drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++++ > > drivers/gpu/drm/i915/display/intel_lvds.c | 5 +++++ > > drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +++++++- > > drivers/gpu/drm/i915/display/intel_tv.c | 8 +++++++- > > drivers/gpu/drm/i915/display/vlv_dsi.c | 18 +++++++++++++++++- > > 12 files changed, 79 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > > index 481fcb650850..ac456a2275db 100644 > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > > @@ -1440,6 +1440,13 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state, > > static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, > > struct drm_display_mode *mode) > > { > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > + enum drm_mode_status status; > > + > > + status = intel_cpu_transcoder_mode_valid(i915, mode); > > + if (status != MODE_OK) > > + return status; > > + > > /* FIXME: DSC? */ > > return intel_dsi_mode_valid(connector, mode); > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c > > index 0e33a0523a75..abaacea5c2cc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_crt.c > > +++ b/drivers/gpu/drm/i915/display/intel_crt.c > > @@ -348,8 +348,13 @@ intel_crt_mode_valid(struct drm_connector *connector, > > struct drm_device *dev = connector->dev; > > struct drm_i915_private *dev_priv = to_i915(dev); > > int max_dotclk = dev_priv->max_dotclk_freq; > > + enum drm_mode_status status; > > int max_clock; > > > > + status = intel_cpu_transcoder_mode_valid(dev_priv, mode); > > + if (status != MODE_OK) > > + return status; > > + > > if (mode->flags & DRM_MODE_FLAG_DBLSCAN) > > return MODE_NO_DBLESCAN; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 5cf162628b95..23b077f43614 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7734,6 +7734,16 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev, > > mode->vtotal > vtotal_max) > > return MODE_V_ILLEGAL; > > > > + return MODE_OK; > > +} > > + > > +enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, > > + const struct drm_display_mode *mode) > > +{ > > Overall the patch looks fine, even if it's a bit meh we have to > duplicate the calls so much. No way around that I guess. > > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > > But please explain the intel_cpu_transcoder_mode_valid() naming. I'm not > sure I follow. These limits (suposedly) only apply to the normal transcoders but not to the BXT/GLK DSI transcoders. > > > > -- > Jani Nikula, Intel -- Ville Syrjälä Intel
