> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Vinod Govindapillai
> Sent: Friday, November 10, 2023 11:32 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Syrjala, Ville <ville.syrjala@xxxxxxxxx>
> Subject: [PATCH v1 1/1] drm/i915/xe2lpd: remove the FBC restriction if PSR2 is enabled
>
> In earlier versions, FBC was restricted if PSR2 is enabled. From xe2lpd onwards no such restrictions are needed anymore.
>
> HSD: 14014305387
FBC + PSR2 can co-exist for xe2lpd.
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index bde12fe62275..f3d572d54e82 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1201,7 +1201,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
> * Recommendation is to keep this combination disabled
> * Bspec: 50422 HSD: 14010260002
> */
> - if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
> + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
> plane_state->no_fbc_reason = "PSR2 enabled";
> return 0;
> }
> --
> 2.34.1
