On Fri, Nov 17, 2023 at 04:44:46PM -0800, Matt Roper wrote:
> This workaround now applies to all variants of DG2 so move it to the
> corresponding block.
>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Actually let's hold on this patch for now...I'm seeing some conflicting
information indicating that maybe we don't actually want/need this
workaround on any DG2 variant. I'm trying to get clarification from the
hardware teams.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9bc0654efdc0..038d4902b6f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2347,6 +2347,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> */
> wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
> LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
> +
> + /* Wa_22014600077:dg2 */
> + wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
> + _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
> + 0 /* Wa_14012342262 write-only reg, so skip verification */,
> + true);
> }
>
> if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> @@ -2357,14 +2363,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> 0, true);
> }
>
> - if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {
> - /* Wa_22014600077:dg2 */
> - wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
> - _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
> - 0 /* Wa_14012342262 write-only reg, so skip verification */,
> - true);
> - }
> -
> if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /*
> --
> 2.41.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
