== Series Details == Series: series starting with [1/4] drm/i915: move *_crtc_clock_get() to intel_dpll.c URL : https://patchwork.freedesktop.org/series/126345/ State : warning == Summary == Error: dim checkpatch failed 55d6d32443b1 drm/i915: move *_crtc_clock_get() to intel_dpll.c -:342: CHECK:BRACES: braces {} should be used on all arms of this statement #342: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:458: + if (dpll & PLL_P1_DIVIDE_BY_TWO) [...] + else { [...] -:344: CHECK:BRACES: Unbalanced braces around else statement #344: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:460: + else { total: 0 errors, 0 warnings, 2 checks, 424 lines checked efebb37b3248 drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY() -:53: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #53: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:120: } +static inline enum dpio_phy vlv_pipe_to_phy(enum pipe pipe) total: 0 errors, 0 warnings, 1 checks, 71 lines checked 8ab424cf9c80 drm/i915: convert vlv_dpio_read()/write() from pipe to phy -:356: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #356: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:953: + vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data << DPIO_UPAR_SHIFT); -:431: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #431: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1062: + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port), uniqtranscale_reg_value); -:460: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #460: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1088: + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), DPIO_PCS_TX_LANE2_RESET | -:464: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #464: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1091: + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | -:664: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #664: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1899: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), 0x009f0003); -:668: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #668: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1902: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), 0x00d0000f); -:675: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #675: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1908: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 0x0df40000); -:679: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #679: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1911: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 0x0df70000); -:685: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #685: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1916: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 0x0df70000); -:689: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #689: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1919: + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), 0x0df40000); -:719: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #719: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1997: + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port), 5 << DPIO_CHV_S1_DIV_SHIFT | -:731: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #731: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:2007: + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port), DPIO_CHV_M1_DIV_BY_2 | -:779: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #779: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:2062: + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), + vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) | total: 0 errors, 0 warnings, 13 checks, 807 lines checked b0ffb7a14cd9 drm/i915: move sideband regs to vlv_sideband_reg.h
