> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, November 7, 2023 9:48 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>
> Subject: [PATCH 3/4] drm/i915/dp_mst: Use helpers to get dsc
> min/max input bpc
>
> Use helpers for source min/max input bpc with DSC.
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++++-------
> 3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5adab761f2e8..abc718f1a878 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1566,7 +1566,6 @@ intel_dp_compute_link_config_wide(struct intel_dp
> *intel_dp,
> return -EINVAL;
> }
>
> -static
> u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) {
> if (!HAS_DSC(i915))
> @@ -1946,7 +1945,6 @@ static int dsc_compute_compressed_bpp(struct
> intel_dp *intel_dp,
> dsc_max_bpp, dsc_min_bpp,
> pipe_bpp, timeslots); }
>
> -static
> u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) {
> /* Min DSC Input BPC for ICL+ is 8 */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 484aea215a25..53e88c00900c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -164,5 +164,7 @@ intel_dp_compute_config_link_bpp_limits(struct
> intel_dp *intel_dp,
> struct link_config_limits *limits);
>
> void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector
> *connector);
> +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915);
> +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7b4628f4f124..d32e5258e1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -194,18 +194,15 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> int i, num_bpc;
> u8 dsc_bpc[3] = {};
> int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
> - u8 dsc_max_bpc;
> + u8 dsc_max_bpc, dsc_min_bpc;
> bool need_timeslot_recalc = false;
> u32 last_compressed_bpp;
>
> - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
> - if (DISPLAY_VER(i915) >= 12)
> - dsc_max_bpc = min_t(u8, 12, conn_state-
> >max_requested_bpc);
> - else
> - dsc_max_bpc = min_t(u8, 10, conn_state-
> >max_requested_bpc);
> + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
> + dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
>
> max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
> - min_bpp = limits->pipe.min_bpp;
> + min_bpp = max_t(u8, dsc_min_bpc * 3, limits->pipe.min_bpp);
>
> num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector-
> >dp.dsc_dpcd,
> dsc_bpc);
> --
> 2.40.1
