Hi Ville,
On Mon, 2023-11-06 at 22:12 +0200, Ville Syrjälä wrote:
> On Thu, Nov 02, 2023 at 11:55:18PM +0200, Vinod Govindapillai wrote:
> > If both PSR2 + FBC is supported, in cases where the selective
> > fetch area is greater than 25% of the screen area, FBC might
> > be more efficient.
>
> "might be more efficient" is a very weak justification.
That is a poor choice of wording from me! I will update!
The feature HAS has documented power assessment information
BR
Vinod
>
> This sort of stuff would really need to be accompanied by
> some actual power numbers (for some actually reasonable
> workloads) to justify the extra complication.
>
> > So have a possibility to check this and add
> > provision to enable FBC in such cases.
> >
> > Bspec: 68881
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx>
> > ---
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 42 ++++++++++++++++---
> > 2 files changed, 38 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 047fe3f8905a..bcc5fd8d8a00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1207,6 +1207,7 @@ struct intel_crtc_state {
> > bool has_psr;
> > bool has_psr2;
> > bool enable_psr2_sel_fetch;
> > + bool full_frame_fetch;
> > bool req_psr2_sdp_prior_scanline;
> > bool wm_level_disabled;
> > u32 dc3co_exitline;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index ecd24a0b86cb..6cb32fd29d10 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1987,10 +1987,35 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct
> > intel_crtc_state *c
> > return true;
> > }
> >
> > +/*
> > + * Check selective fetch is optimum
> > + *
> > + * Compare selective fetch area w.r.t screen size in case both FBC and PSR2
> > + * is supported. If the selective fetch area is more than 25% of screen
> > + * size, FBC is might be more efficient than PSR2. So force full frame
> > + * update.
> > + */
> > +static bool psr2_sel_fetch_not_optimal(struct drm_i915_private *i915,
> > + struct drm_rect *sel_fetch,
> > + struct drm_rect *src)
> > +{
> > + int screen_area, selfetch_area;
> > +
> > + /* This is needed where FBC + PSR can be supported */
> > + if (DISPLAY_VER(i915) < 20 || !i915->display.params.enable_fbc ||
> > + !HAS_FBC(i915))
> > + return false;
> > +
> > + selfetch_area = drm_rect_height(sel_fetch) * drm_rect_width(sel_fetch);
> > + screen_area = drm_rect_height(src) * drm_rect_width(src);
> > +
> > + return DIV_ROUND_CLOSEST(screen_area, selfetch_area) <= 4;
> > +}
> > +
> > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
> > struct intel_plane_state *new_plane_state, *old_plane_state;
> > @@ -2082,7 +2107,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > * calculation for those.
> > */
> > if (pipe_clip.y1 == -1) {
> > - drm_info_once(&dev_priv->drm,
> > + drm_info_once(&i915->drm,
> > "Selective fetch area calculation failed in pipe %c\n",
> > pipe_name(crtc->pipe));
> > full_update = true;
> > @@ -2092,9 +2117,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > goto skip_sel_fetch_set_loop;
> >
> > /* Wa_14014971492 */
> > - if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> > - IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> > - crtc_state->splitter.enable)
> > + if ((IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> > + IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915)) &&
> > + crtc_state->splitter.enable)
> > pipe_clip.y1 = 0;
> >
> > ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> > @@ -2149,7 +2174,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > }
> > }
> >
> > + if (full_update)
> > + goto skip_sel_fetch_set_loop;
> > +
> > + full_update = psr2_sel_fetch_not_optimal(i915, &pipe_clip,
> > + &crtc_state->pipe_src);
> > +
> > skip_sel_fetch_set_loop:
> > + crtc_state->full_frame_fetch = full_update;
> > psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> > return 0;
> > }
> > --
> > 2.34.1
>
