On Wed, Sep 25, 2013 at 02:04:32PM -0700, Jesse Barnes wrote: > Still digging up the actual VBT info for this, but wanted to get this > out there for testing, or in case others are also bugged by this. > > This can happen if you boot with an external display connected. In that > case, the attached eDP backlight modulation frequency may not be > programmed, so we need to use something (in this case the value my BIOS > normally programs with just the internal display enabled). > > v2: fix masking and magic value in read_blc_pwm_ctl (Jani) > > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67732 Tested-by: shui yangwei <yangweix.shui@xxxxxxxxx> (v1) > --- > drivers/gpu/drm/i915/intel_panel.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index 8f025c6..5468416 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -372,6 +372,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) > I915_WRITE(BLC_PWM_CTL2, > dev_priv->regfile.saveBLC_PWM_CTL2); > } > + > + if (IS_VALLEYVIEW(dev) && !val) > + val = 0x0f42ffff; > } > > return val; > @@ -629,10 +632,24 @@ set_level: > spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); > } > > +/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */ > +static void intel_panel_init_backlight_regs(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + if (IS_VALLEYVIEW(dev)) { > + u32 cur_val = I915_READ(BLC_PWM_CTL) & > + BACKLIGHT_DUTY_CYCLE_MASK; > + I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val); > + } > +} > + > static void intel_panel_init_backlight(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > + intel_panel_init_backlight_regs(dev); > + > dev_priv->backlight.level = intel_panel_get_backlight(dev); > dev_priv->backlight.enabled = dev_priv->backlight.level != 0; > } > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
