Hi Jonathan, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jonathan > Cavitt > Sent: Thursday, November 2, 2023 10:59 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Gupta, saurabhg <saurabhg.gupta@xxxxxxxxx>; Cavitt, Jonathan > <jonathan.cavitt@xxxxxxxxx>; chris.p.wilson@xxxxxxxxxxxxxxx > Subject: [PATCH] drm/i915/gt: Temporarily disable CPU caching into > DMA for MTL > > FIXME: It is suspected that some Address Translation Service (ATS) > issue on IOMMU is causing CAT errors to occur on some MTL workloads. > Applying a write barrier to the ppgtt set entry functions appeared > to have no effect, so we must temporarily use I915_MAP_WC in the > map_pt_dma class of functions on MTL until a proper ATS solution is > found. > What is the performance impact here? Are we disabling caching only for the pte changes/scratch pages or does it extend beyond? Regards, Radhakrishna(RK) Sripada > Signed-off-by: Jonathan Cavitt <jonathan.cavitt@xxxxxxxxx> > CC: Chris Wilson <chris.p.wilson@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_gtt.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c > b/drivers/gpu/drm/i915/gt/intel_gtt.c > index 4fbed27ef0ecc..21719563a602a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > @@ -95,6 +95,16 @@ int map_pt_dma(struct i915_address_space *vm, struct > drm_i915_gem_object *obj) > void *vaddr; > > type = intel_gt_coherent_map_type(vm->gt, obj, true); > + /* > + * FIXME: It is suspected that some Address Translation Service (ATS) > + * issue on IOMMU is causing CAT errors to occur on some MTL > workloads. > + * Applying a write barrier to the ppgtt set entry functions appeared > + * to have no effect, so we must temporarily use I915_MAP_WC here on > + * MTL until a proper ATS solution is found. > + */ > + if (IS_METEORLAKE(vm->i915)) > + type = I915_MAP_WC; > + > vaddr = i915_gem_object_pin_map_unlocked(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > @@ -109,6 +119,16 @@ int map_pt_dma_locked(struct i915_address_space > *vm, struct drm_i915_gem_object > void *vaddr; > > type = intel_gt_coherent_map_type(vm->gt, obj, true); > + /* > + * FIXME: It is suspected that some Address Translation Service (ATS) > + * issue on IOMMU is causing CAT errors to occur on some MTL > workloads. > + * Applying a write barrier to the ppgtt set entry functions appeared > + * to have no effect, so we must temporarily use I915_MAP_WC here on > + * MTL until a proper ATS solution is found. > + */ > + if (IS_METEORLAKE(vm->i915)) > + type = I915_MAP_WC; > + > vaddr = i915_gem_object_pin_map(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > -- > 2.25.1
