On Tue, Oct 24, 2023 at 04:09:05AM +0300, Imre Deak wrote:
> Enable FEC in crtc_state, as soon as it's known it will be needed by
> DSC. This fixes the calculation of BW allocation overhead, in case DSC
> is enabled by falling back to it during the encoder compute config
> phase (vs. enabling FEC due to DSC being enabled on other streams).
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dp.h | 5 +++++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++++
> 3 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1891c0cc187d1..2048649b420b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1369,9 +1369,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> return false;
> }
>
> -static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> - const struct intel_connector *connector,
> - const struct intel_crtc_state *pipe_config)
> +bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> + const struct intel_connector *connector,
> + const struct intel_crtc_state *pipe_config)
> {
> return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
> drm_dp_sink_supports_fec(connector->dp.fec_capability);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 484aea215a251..0258580a6aadc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -137,6 +137,11 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> }
>
> u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
> +
> +bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> + const struct intel_connector *connector,
> + const struct intel_crtc_state *pipe_config);
> +
> u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
>
> void intel_ddi_update_pipe(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 80b3df6d51fc8..98d775d862ac4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -338,6 +338,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_dp *intel_dp = &intel_mst->primary->dp;
> + const struct intel_connector *connector =
> + to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> struct link_config_limits limits;
> @@ -380,6 +382,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> &limits))
> return -EINVAL;
>
> + if (!intel_dp_supports_fec(intel_dp, connector, pipe_config))
> + return -EINVAL;
> +
> + pipe_config->fec_enable = !intel_dp_is_uhbr(pipe_config);
The above is bogus, since pipe_config->port_clock will be set only later
in intel_dp_mst_find_vcpi_slots_for_bpp(). I'll send an updated version
moving the above later to that function.
> +
> /*
> * FIXME: As bpc is hardcoded to 8, as mentioned above,
> * WARN and ignore the debug flag force_dsc_bpc for now.
> --
> 2.39.2
>
