On Tue, Oct 24, 2023 at 04:09:15AM +0300, Imre Deak wrote:
> Disable the FEC ready flag in the sink during a disabling modeset.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6f9d0f2ff3d9a..99d96762fa29c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2211,18 +2211,21 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
> }
>
> static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> + const struct intel_crtc_state *crtc_state,
> + bool enable)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> if (!crtc_state->fec_enable)
> return;
>
> - if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
> - drm_dbg_kms(&i915->drm,
> - "Failed to set FEC_READY in the sink\n");
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
> + enable ? DP_FEC_READY : 0) <= 0)
> + drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n",
> + enable ? "enabled" : "disabled");
>
> - if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
> + if (enable &&
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
> DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
> drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n");
> }
> @@ -2541,7 +2544,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * in the FEC_CONFIGURATION register to 1 before initiating link
> * training
> */
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
>
> intel_dp_check_frl_training(intel_dp);
> intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> @@ -2692,7 +2695,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * in the FEC_CONFIGURATION register to 1 before initiating link
> * training
> */
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
>
> intel_dp_check_frl_training(intel_dp);
> intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> @@ -2768,7 +2771,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> true);
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);
> intel_dp_start_link_train(intel_dp, crtc_state);
> if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
> !is_trans_port_sync_mode(crtc_state))
> @@ -2997,6 +3000,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>
> intel_disable_ddi_buf(encoder, old_crtc_state);
>
> + intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);
> +
> /*
> * From TGL spec: "If single stream or multi-stream master transcoder:
> * Configure Transcoder Clock select to direct no clock to the
> --
> 2.39.2
>
