> > > > This sounds like there's some sort of MFD rather than or as well as a flash > > > chip, or possibly multiple SPI devices? > > > Yes, the driver doesn't talk to SPI controller directly it goes via > > another layer, so all SPI standard HW is not accessible, but we wish > > to expose the MTD interface. > > Perhaps if you described clearly and directly the actual system you are > trying to model then it would be easier to tell how it fits into the > kernel? What is the actual interface here - how does the host interact > with the flash? > > Also to repeat: please fix your mail client to word wrap within > paragraphs at something substantially less than 80 columns. Doing this > makes your messages much easier to read and reply to. Sorry for that, I'm fairly new in SPI and MTD subsystems. Will try to describe as best as I could. There is a Discreet Graphic device with embedded SPI (controller & flash). The embedded SPI is not visible to OS. There is another HW in the chip that gates access to the controller and exposes registers for: region select; read and write (4 and 8 bytes); erase (4K); error register; There are two main usages - user-space manufacturing and repair application that requires unrestricted read/write/erase over flash chip and kernel module that requires read access to one of flash regions for configuration. -- Alexander (Sasha) Usyskin CSE FW Dev - Host SW Intel Israel (74) Limited
