2013/9/20 Daniel Vetter <daniel@xxxxxxxx>: > On Thu, Sep 19, 2013 at 09:24:33PM +0100, Chris Wilson wrote: >> On Thu, Sep 19, 2013 at 05:03:06PM -0300, Paulo Zanoni wrote: >> > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >> > >> > At the end of haswell_crtc_enable we have an intel_wait_for_vblank >> > with a big comment, and the message suggests it's a workaround for >> > something we don't really understand. So I removed that wait and >> > started getting HW state readout error messages saying that the IPS >> > state is not what we expected. >> > >> > I investigated and concluded that after you write IPS_ENABLE to >> > IPS_CTL, the bit will only actually become 1 on the next vblank. So >> > add code to wait for the IPS_ENABLE bit. We don't really need this >> > wait right now due to the wait I already mentioned, but at least this >> > one has a reason to be there, while the other one is just to >> > workaround some problem: we may remove it in the future. >> > >> > The wait also acts as a POSTING_READ which we missed. >> > >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >> >> Both patches: >> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> >> >> I was thinking that maybe the intel_wait_for_vblank would be better from >> a documenting perspective - and it would also give warnings for trying >> to enable ips whilst the pipe was off. But you would still need the wait >> for IPS_ENABLE as confirmation anyway. > > Both queued for -next, thanks for the patches&review. Hmmm, this patch depends on the "enable planes only after the pipe is really running" patch. Due to that missing patch, now I get "[drm:hsw_enable_ips] *ERROR* Timed out waiting for IPS enable" when booting. I should have said this, sorry :( I > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
